Conventional 6T-2port (6 transistors-2-port) SRAM cells generally suffer from dummy read disturb in write operation. For example, a signal (e.g., signal RWWL) is used for both reading and writing, and this signal RWWL controls all memory cells in the same row. As a result, when signal RWWL is activated to write to a cell (e.g., cell W), for example, this signal RWWL not only activates the cell to be written W but also affects other cells in the same row (e.g., cells R). In effect, a “dummy” read operation is performed on these cells R, which can disturb the write operation, including, for example, reducing the noise margin of the cross latch storing data for the memory.
8T-2 port SRAMs in which a read operation is performed before writing may be used to avoid the above deficiencies. As a result, in a write cycle, there are two operations including first reading the data then latching the data to be written into the cell. To achieve this read-first then write operation, the approach uses column-based sense amplifiers in which each column includes an inverter sense amplifier being coupled to all cells in that column. Because the inverter sense amplifier is coupled to all cells in a column, if one cell is activated, other un-activated (e.g., unselected) cells can be affected. Further, because the approach requires a read operation before writing, the write operation timing is degraded (e.g., long) as additional time in the same cycle is needed for reading. The approach also requires a D-latch to latch the written data, which adds complexity (e.g., control signal for the latch, etc.) and additional layout areas to the circuitry.
Like reference symbols in the various drawings indicate like elements.